For decades, capacitors have been an important and irreplaceable circuit element used often in semiconductor circuit designs. For example, capacitors are widely used in applications such as a dynamic random access memory (DRAM), active and passive filters, analog-to-digital (A/D) and digital-to-analog (D/A) converters, operational amplifiers, radio and tuning circuits, oscillators and multivibrator circuits, time critical and time delay circuitry, noise reduction circuitry, charge pumps, power electronics, and many other diverse applications. A capacitor is defined in the simplest terms as a device consisting of two conducting surfaces separated by an insulating material. A capacitor stores electrical energy or charge, blocks the flow of direct current (DC), and permits the flow of alternating current (AC) depending essentially upon the capacitance of the device and the frequency of the incoming current or charge.
Capacitance, measured in farads, is determined by three physical characteristics: (1) a thickness or average thickness of the insulating material separating the two conducting surfaces; (2) how much surface area is covered by the two conducting surfaces; and (3) various mechanical and electrical properties of the insulating material and the two conducting surfaces. Achieving a high capacitance value while reducing substrate surface area is necessary for future generations of integrated circuits.
In the early development and marketing of the above mentioned technologies, parallel plate or parallel electrode capacitors were used as a capacitance structure. The parallel electrode capacitor is a capacitor which has a planar top conducting surface and a planar bottom conducting surface separated by a planar dielectric or insulator. Because the parallel electrode capacitor is completely planar, large surface areas of substrate material or substrate-overlying layers of material are consumed to achieve capacitance values in a useful nanofarad or picofarad range.
DRAM memory cells are electronic circuits that are used to store a bit of binary information. DRAM memory cell substrate area reduction is very critical in order to achieve device densities that allow for a DRAM integrated circuit with a large amount of memory cells. To achieve DRAM memory circuits with a million bits of storage or more, the industry developed a trench capacitor. The trench capacitor is formed by first etching a deep well, trench, or hole in a substrate surface or a surface overlying the substrate surface. A sidewall surface of the trench or hole is used to form a first electrode. The first electrode is covered by a dielectric material, and a second electrode is formed overlying the dielectric material. The second electrode usually completely fills the trench. Due to the fact that the sidewalls of the trench or hole provide surface area to the trench capacitor without consuming additional substrate surface area, the trench capacitor reduces capacitor substrate surface area and reduces the size of standard DRAM memory cells. Although the trench capacitor resulted in reductions in surface area, other advances in the technology are required to achieve further advances in DRAM technology.
In order to achieve further reduction in DRAM cell sizes, a fin capacitor was developed. The fin capacitor is formed by creating a first electrode overlying the substrate surface which resembles a vertically oriented comb-like structure. A central vertical pillar or spine of conducting material electrically connects to several horizontally positioned fins or planes of conducting material to form the comb-like structure. A second electrode is formed overlying the substrate in a vertical comb-like structure similar to the first electrode. The one difference between the two comb-like structures is that the fins of the first structure separate the fins of the second structure, or in other words, the fins from the two structures are intertwined thereby maximizing the surface area that the fins contribute to device capacitance. The fin capacitor device tended to be very complex to manufacture and also limiting due to its geometric shape and fabrication scheme.
In order to further improve area savings and reduce overlying layer complexity, a "double box" capacitor and other vertically raised capacitors were developed. The double box capacitor is created by lithographically forming a first box of conductive material with four sides. The four sides of this first box, which rise vertically above the surface of the substrate, surround a solid vertical lithographically-defined second box of conductive material. The first and second boxes are electrically connected to form a bottom electrode. An insulator covers the first and second boxes, and an overlying conductive layer forms the second capacitor electrode. In addition, structures similar to the double box capacitor have been taught.
Although DRAM cells may be manufactured using the capacitors mentioned above, the DRAM cells are: (1) limited largely by lithography; (2) in most cases lithographically intensive; (3) not space efficient enough for future memory generations; (4) likely to have topographical problems due to large differences in height across the capacitive devices; and (5) increasingly difficult to manufacture and mechanically unstable as topography increases.
Other devices, such as transistors, are area intensive and must also be reduced in surface area in order to improve DRAM cell circuit density. A surrounding gate transistor (SGT) is used to reduce transistor substrate surface area. The SGT uses a sidewall gate electrode and trench etch technology to reduce the gate electrode surface area.